EE140 Course Notes: Analog Integrated Circuits and an LCD Driver Amplifier

In spring 2024 I took EE140 (Linear Integrated Circuits) at Berkeley, with Razavi's Design of Analog CMOS Integrated Circuits as the textbook. The course starts from single-transistor amplifiers, moves through current mirrors, differential pairs, frequency response, and feedback, and ends with two-stage op amps and compensation. Every lab builds schematics and runs simulations in Cadence Virtuoso, and the final project designs a pixel driver amplifier for a smartwatch LCD. Lab reports, design scripts, and the project report are collected in 2024_spring_ee140.

Labs

Lab 1: Cadence and the common-source amplifier. The lab builds the schematic, symbol, and testbench of a common-source amplifier and annotates its DC operating point. For a long-channel MOSFET in saturation, the small-signal gain is

\[ A_v = -g_m r_{out}, \qquad g_m = \frac{2I_D}{V_{GS}-V_{th}}, \qquad r_{out} \approx \frac{1}{\lambda I_D}, \]

and multiplying the terms gives \(A_v \approx -\dfrac{2}{\lambda (V_{GS}-V_{th})}\). A transistor biased in saturation provides gain because \(V_{GS}\) controls its drain current while \(V_{DS}\) barely affects it, and because its output resistance is large.

Lab 2: hand analysis against simulation. The lab uses HSPICE level 3 models with threshold voltages of 0.8 V for NMOS and −0.8 V for PMOS. For two circuit configurations, I first calculated the gain and bandwidth by hand and then ran AC and transient simulations in Cadence to compare gain, bandwidth, and output swing. For the first configuration, the hand analysis gives a gain of about 19.3 dB and a bandwidth of about 1.9 MHz.

Lab 3: the \(g_m/I_D\) design method. This lab sizes devices from simulated lookup tables instead of the square-law model. Exercise 1 fixes a load capacitance \(C_L = 1\) pF, a unity-gain bandwidth \(f_u = 1\) GHz, \(g_m/I_D = 15\) S/A, and a channel length \(L = 100\) nm, and the design proceeds in three steps:

\(g_m = 2\pi f_u C_L\) gives the required transconductance of about 6.28 mS.
\(I_D = g_m / (g_m/I_D)\) gives a bias current of about 419 µA.
The lookup table gives the current density \(J_D\) at this \(g_m/I_D\) and channel length, and \(W = I_D / J_D\) gives the device width.

The same table also gives the intrinsic gain \(g_m/g_{ds}\) and the transit frequency \(f_T\), which check whether the chosen channel length meets the gain and speed targets together. The later exercises extend the procedure to differential pairs, where the input common-mode level adds constraints on the tail device and the load resistors.

Final project: an LCD pixel driver amplifier

The project designs a pixel driver amplifier for a 38 mm smartwatch display with 272 × 340 pixels refreshed at 60 Hz. The amplifier takes its input from an ideal 10-bit DAC with a 0.7 V full scale, the hardest transition is a full 1.4 V swing, and the pixel load is modeled as 400 Ω in series with 60 pF.

Settling time and gain budget. The amplifier drives every pixel in sequence within one refresh period, so each pixel gets a settling time of

\[ T_{settle} = \frac{1}{60 \times 272 \times 340} \approx 180.22 \text{ ns}. \]

I split the 0.2% total error into 0.1% static error and 0.1% dynamic error. The static error \(\varepsilon_s = 1/(1+\beta A_{DC})\) sets the DC gain, and with the feedback factor in my report \(A_{DC}\) needs to reach about 2997. The dynamic error \(\varepsilon_d = e^{-T_{settle}/\tau}\) sets the closed-loop time constant:

\[ \tau = \frac{T_{settle}}{\ln(1/\varepsilon_d)} = \frac{180 \text{ ns}}{\ln 1000} \approx 26.05 \text{ ns}. \]

When the compensated loop is approximated as a single-pole system, the unity-gain bandwidth of the loop gain equals the closed-loop dominant pole, so the loop needs a unity-gain angular frequency of \(\omega_u = 1/\tau \approx 3.84 \times 10^7\) rad/s.

Circuit structure. The first stage is an NMOS telescopic cascode amplifier that provides most of the gain. The second stage is a class AB output stage with PMOS inputs that handles the slew rate, and an NMOS source follower between the stages sets the bias, with Miller compensation across them. To keep the phase margin above 45°, the non-dominant pole sits near the unity-gain frequency, which gives the second-stage transconductance \(g_{m2} = \omega_{p2} C_L\), while \(g_{m1} = \omega_u C_C / \beta\) sets the first stage. Device sizing follows the \(g_m/I_D\) procedure from Lab 3: I swept \(g_m/I_D\) and channel length so that \(f_T\) met the bandwidth target with the largest gain, then swept the compensation capacitor \(C_C\) to tune the phase margin.

Results.

Metric	Specification	Design
Settling time	180.22 ns	173 ns
Power	≤ 1.1 mW	482.41 µW
Total capacitance	≤ 2 pF	50 fF
Total resistance	≤ 100 MΩ	100 MΩ
CMRR at DC	≥ 65 dB	70.52 dB
PSRR at DC	≥ 50 dB	59.78 dB
Phase margin	≥ 45°	53.5°

2026.09.28